In the field of integrated circuits, particularly in non-volatile memory devices, it is often necessary to generate on-chip negative voltages starting from the positive voltage supply (VDD) which supplies the integrated circuit. This is for example the case of EEPROMs and Flash EEPROMs, wherein a negative voltage is necessary for the erase operation of the memory cells.
Conventionally, negative voltages are generated on-chip by means of negative charge pumps using P-channel MOSFETs, of the type shown in FIG. 1. With reference to this figure, it is possible to see that the negative charge pump is composed of several stages S1-S4 (four in this example), connected in series between ground and an output terminal O of the charge pump at which a negative voltage is provided. Each stage S1-S4 comprises a P-channel pass transistor M1, a P-channel pre-charge transistor M2, a charge storage capacitor CL driven by a respective first digital signal B or D periodically switching between ground and the voltage supply VDD, and a boost capacitor CP driven by a respective second digital signal A or C substantially in phase opposition with respect to signal B or D; the simplified timing of signals A, B, C and D is depicted in FIG. 2.
In operation, a positive charge flow takes place from the storage capacitor CL of a given stage to the storage capacitor CL of the adjacent, left-hand stage in FIG. 1, through the pass transistors M1, so that the output terminal O acquires a negative potential. The pre-charge transistor M2 pre-charges the boost capacitor CP, which in turn boosts the gate voltage of M1 so as to allow a most efficient charge transfer to take place.
When the negative charge pump is integrated in a CMOS integrated circuit, the P-channel MOSFETs are conventionally formed inside respective N-type wells which are in turn formed inside a common P-type semiconductor substrate.
The main drawbacks of the circuit described above will be now discussed.
First, due to the body effect affecting MOS transistors, a progressive increase in the threshold voltage of the P-channel MOSFETs takes place moving from the stages near to the terminal of the charge pump connected to ground to the stages proximate to the output terminal O. In fact, the N-type wells wherein the P-channel MOSFETs are formed cannot be biased at negative voltages (otherwise the N-type well/P-type substrate junction becomes forward biased), while the source and drain electrodes of the P-channel MOSFETs are biased at more and more negative potentials. This reduces efficiency of the charge pump, because the voltage gain of each stage decreases; this reflects on a higher number of stages being necessary for generating a given negative voltage. Furthermore, the body effect limits the negative voltage value that can be generated, because when the body effect is so high that the threshold voltage of the P-channel MOSFETs reaches the value of the voltage supply VDD, even if more stages are added to the charge pump the negative output voltage cannot increase further (in absolute value).
Second, P-channel MOSFETs are intrinsically slower than N-channel MOSFETs, so that the maximum operating frequency of the charge pump is limited; this has a negative impact on the output current capability of the charge pump.
Third, the charge pump structure shown in FIG. 1 has a poor reliability; in fact, when the pass transistors M1 are off, the voltage applied to their gate oxide is equal to the difference between their gate voltage and the bias voltage of the N-type wells inside which the transistors are formed; the gate voltage can go strongly negative (especially in the final stages of the charge pump), but the bias voltage of the N-type wells cannot be lower than 0 V (to prevent forward biasing of the N-type wells/P-type substrate junctions).
Fourth, conventional CMOS manufacturing process could easily provide N-channel MOSFETs which are more resistant to junction breakdown than their P-channel counterparts; in this case, the reliability of the charge pump is lower relative to using N-channel MOSFETS.